1. Field of the Invention
The present invention relates to a symbol timing recovery method and apparatus in a television receiver. More specifically, the present invention relates to a symbol timing recovery method apparatus useful in a high definition digital television receiver.
2. Discussion of the Related Art
Any terrestrial digital TV system must perform a number of functions, and overcome a number of problems, in transmitting signals to a receiver. For example, the United States has adopted the Advanced Television System Committee (ATSC) System using eight level vestigial sideband (8-VSB) as its digital television modulation standard. In this system, data representing the television program is transmitted as a stream of symbols, each symbol representing three data bits. These symbols are generated at a specified nominal frequency.
The recovery of data from modulated signals containing digital information in symbol stream form usually requires three functions at a receiver: timing recovery for symbol synchronization, carrier recovery (frequency demodulation to baseband) and channel equalization. The present invention deals specifically with a method and apparatus for more reliable and faster acquisition of symbol timing recovery (STR) over a wider range of STR offset frequencies.
The symbol timing recovery is a process by which a receiver symbol clock (timebase) is synchronized to the transmitter symbol clock. It permits a received signal to be sampled at optimum points in time to reduce slicing errors associated with decision-directed processing of received symbol values. It is therefore an important purpose of the present invention to provide a timing recovery loop for obtaining symbol synchronization. In order to lock the receiver symbol sampling frequency to the transmitted symbol frequency, the symbol frequency must be acquired, estimated and tracked so that samples can be taken at the correct rate and locations in time. For example, though the system symbol rate can be specified to be 20 megahertz (MHz), the respective frequencies of the oscillators in both the transmitter and the receiver may drift with time and thus the actual symbol frequency differentiate from the specified symbol frequency. The difference between the actual symbol frequency of the received signal and the specified symbol frequency is termed ‘offset’ in the remainder of this application.
In a known embodiment of a symbol timing recovery circuit, a phase locked loop (PLL) in the receiver generates the symbol clock in synchronism with the received signal. The PLL includes a loop integrator which controls the frequency of a voltage controlled oscillator. A phase comparator, comparing the respective phases of the received signal and the output signal of the voltage controlled oscillator, provides a control signal to the loop integrator, all in a known manner. When a new signal is to be received, the output of the loop integrator must be adjusted such that the frequency of the voltage controlled oscillator is matched to the symbol rate of the new signal, a process termed acquisition.
The PLL must be able to lock to a range of symbol frequency values in order to receive signals from different transmitters each having their own transmitter clock. As described above, the symbol frequency of the received signal will often be offset from the specified symbol frequency. Equivalently, the term offset may refer to the difference between the value of the loop integrator signal which would condition the loop oscillator to generate a signal locked to the symbols in the received signal and the value of the loop integrator signal which would condition the loop oscillator to generate a signal locked to symbols at the specified frequency.
There are several problems involved with achieving appropriate symbol timing recovery in the receiver. For example, it may take a long time for the symbol timing recovery circuit to acquire a “lock” on a channel if the starting point of the symbol timing recovery (STR) loop integrator (e.g. the loop integrator output signal for the previous signal) is far away from the eventual locked value for the new signal. The problem becomes even more serious when a narrow STR loop bandwidth is utilized in order to insure reliable acquisition. Indeed, if the STR starting offset is too far away from the locked value, STR loop lock may not be reliably achieved at all. Also, under moderate to strong ghost conditions, symbol timing lock is more reliably achieved when the starting offset is close to the final offset.